IBM has announced a groundbreaking advancement in semiconductor technology, unveiling what it describes as the world’s first sub-1 nanometer chip technology. The new architecture, named “nanostack,” can integrate nearly 100 billion transistors on a chip the size of a human fingernail — nearly twice the transistor density of IBM’s previous generation of chip technology. The resulting improvements in compute performance and energy efficiency are poised to transform AI data centers and other demanding computing environments.
“It’s not just an incremental step, it’s a meaningful leap forward,” said Jay Gambetta, director of IBM Research and IBM Fellow, during an advance media briefing. He described the new chip technology as “pointing to a future where computing becomes significantly more powerful without a corresponding increase in energy.” The announcement was made in conjunction with presentations at the 2025 IEEE Symposium on VLSI Technology and Circuits held in Kyoto, Japan.
Understanding the sub-1 nanometer claim
The phrase “sub-1 nanometer chip technology” requires careful explanation. It is physically impractical to build reliably functional chips with transistors and other features smaller than 1 nanometer due to fundamental physical limitations, such as quantum tunneling and heat dissipation. Instead, IBM’s claim is based on the performance improvements that would be expected if a theoretical chip could be built with such tiny features. The company designates its new technology as the 0.7-nanometer node, also referred to as the 7 angstrom node (since 1 nanometer equals 10 angstroms).
However, these node numbers have not corresponded to actual physical dimensions for decades. In the 1970s and 1980s, chip process nodes like 180nm matched the actual gate length of transistors. But starting around the 90nm node, chipmakers began using node names to indicate generations of technology rather than precise physical sizes. Today, a 3nm or 2nm node chip does not have transistors only 3 or 2 nanometers wide; the names refer to equivalent performance scaling compared to historical nodes. IBM’s 0.7nm node is similarly a marker of performance gains, not a literal measurement.
Nanostack architecture: stacking transistors vertically
To overcome the physical scaling limits that have plagued Moore’s Law in recent years, IBM’s nanostack architecture vertically stacks transistors in a staggered layout. This allows more transistors to be packed into the same chip area without shrinking individual transistor dimensions. The nanostack builds on IBM’s previous innovations in nanosheet transistors, which themselves represented a major shift from traditional finFET designs. IBM introduced its 2-nanometer node nanosheet technology in 2021.
The basic unit of the nanostack architecture consists of two transistors stacked and bonded together. Each transistor comprises three nanosheets that are individually 5 nanometers thick — equivalent to about 15 rows of silicon atoms. There is also a distance of about 9 nanometers separating each nanosheet. This vertical stacking approach is analogous to constructing a multi-story building on the same footprint, dramatically increasing transistor density without requiring ever-finer lithography.
Performance gains for the AI era
According to projections from IBM’s published technical reports, the nanostack architecture could deliver 50% higher computing performance or 70% greater energy efficiency compared to the company’s previous 2-nanometer node chips. These gains are critical for AI workloads, which demand massive parallel computation and fast data access. At the VLSI Symposium, IBM researchers also demonstrated a 40% improvement in scaling for static random-access memory (SRAM), which is essential for storing frequently accessed data in CPUs and GPUs.
SRAM allows fast but energy-intensive read and write operations. Many AI accelerators rely on large SRAM caches to reduce latency and improve throughput. The improvement in SRAM scaling is made possible through a staggered-channel design for the chip’s SRAM bit cells — memory storage units consisting of six transistors — that reduces overall cell height by 40% and enables more SRAM to be squeezed into the same chip space. This will be welcome news for chip designers, as SRAM scaling has fallen off drastically in recent generations. For example, SRAM scaling improved only a few percent between the 3-nanometer chip generation and the 2-nanometer chip generation, Gambetta explained. “This achievement of 40 percent will eventually industrialize itself in AI workflows, which require higher bandwidth and high efficiency,” he said.
The roadmap for sub-1 nanometer nodes
IBM is primarily a research organization when it comes to chip technology; it does not manufacture commercial chips that would end up in AI data centers or consumer devices. Instead, IBM partners with semiconductor manufacturers such as Rapidus in Japan (to mass produce its 2-nanometer node chips) and Samsung in South Korea (to commercialize related technologies). Other companies have followed IBM’s pioneering work independently; for example, Taiwan’s TSMC developed nanosheet transistors for its own 2-nanometer node process.
“Nanosheet has become the foundation of the next generation of transistor scaling,” said Huiming Bu, vice president of IBM Semiconductors Global R&D and IBM Research, during the media briefing. “Today, nanosheet is adopted by all leading foundries for most of the 3-nanometer chips and all of the 2-nanometer chips.” IBM declined to name specific companies for the sub-1 nanometer technology, but Bu expects that commercial chips incorporating the nanostack architecture could begin production as early as five years from now and most likely within a decade. “It will replace nanosheet as today’s mainstream in leading foundries, whether it’s CPUs or GPUs,” Bu said. “Within a decade, this will become another mainstream that we have invented and helped industry to transform.”
The implications of this technology are vast. AI data centers consume enormous amounts of electricity, and any efficiency gains translate directly into lower operational costs and reduced environmental impact. Moreover, the ability to pack more transistors per chip could enable new capabilities in areas like autonomous systems, natural language processing, and scientific computing. IBM’s announcement also underscores the continued relevance of Moore’s Law, albeit in a reinterpreted form: instead of shrinking transistors horizontally, the industry is now stacking them vertically to sustain progress. The nanostack architecture represents a seminal step in that direction, and its adoption by major foundries could reshape the semiconductor landscape over the next decade.
Source: Ars Technica News